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74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 -- 15 March 2010 Product data sheet
1. General description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input (pin T/R) determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW) enables data from B ports to A ports. When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The parity select input (pin ODD/EVEN) allows the user to generate either an odd or even parity output, depending on the system. Pin PARITY is an output from the generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input when receiving from port B to port A port (pin T/R = LOW). In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH inputs on port A. Pin PARITY output goes to the logic state determined by the setting of pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port A is even, pin PARITY output goes LOW, keeping even parity. In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port B is:
* Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error * Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
2. Features and benefits
I I I I I I Combinational functions in one package Low static and dynamic power dissipation with high speed and high output drive Output capability: +64 mA and -32 mA Power-up 3-state Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: N HBM JESD22-A114F exceeds 2000 V N MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range 74ABT657D 74ABT657DB -40 C to +85 C -40 C to +85 C Name SO24 SSOP24 Description plastic shrink small outline package; 24 leads; body width 5.3 mm Version SOT340-1 SOT355-1 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 Type number
74ABT657PW -40 C to +85 C
TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm
4. Functional diagram
2 A0 1 24 11 T/R OE ODD/EVEN B0 B1 B2 23 22 21 ERROR B3 20 B4 17 B5 16 B6 15 B7 14
001aae826
3 A1
4 A2
5 A3
6 A4
8 A5
9 A6
10 A7 13 12
PARITY
Fig 1.
Logic symbol
1 24 11
0 1
M
0 0 BUS B TO A 1 BUS A TO B 2 2 HIGH Z
G3[EVEN] G4[ODD] 2K = 1,3[EVEN] 1,4[ODD] 0,3[EVEN 0,4]ODD 2 13 12 23 22 21 20 17 16 15 14
001aae827
2 3 4 5 6 8 9 10
0
Fig 2.
IEC logic symbol
74ABT657_3
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Product data sheet
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74ABT657
Octal transceiver with parity generator/checker; 3-state
T/R
1
OE
24
A0
2
23
B0
A1
3
22
B1
A2
4
21
B2
A3
5
20
B3
A4
6
17
B4
A5
8
16
B5
A6
9
15
B6
A7
10
14
B7
ODD/EVEN
11
13
PARITY
12
ERROR
001aae828
Fig 3.
Logic diagram
74ABT657_3
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74ABT657
Octal transceiver with parity generator/checker; 3-state
5. Pinning information
5.1 Pinning
74ABT657
T/R A0 A1 A2 A3 A4 VCC A5 A6 1 2 3 4 5 6 7 8 9 24 OE 23 B0 22 B1 21 B2 20 B3 19 GND 18 GND 17 B4 16 B5 15 B6 14 B7 13 PARITY
001aae825
A7 10 ODD/EVEN 11 ERROR 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2. Symbol T/R A0 to A7 VCC ODD/EVEN ERROR PARITY B0 to B7 GND OE Pin description Pin 1 2, 3, 4, 5, 6, 8, 9, 10 7 11 12 13 23, 22, 21, 20, 17, 16, 15, 14 18, 19 24 Description transmit/receive input A port input/3-state output positive supply voltage parity select input error output in receive mode parity output in transmit mode/input in receive mode B port input/3-state output ground (0 V) output enable input (active LOW)
74ABT657_3
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74ABT657
Octal transceiver with parity generator/checker; 3-state
6. Functional description
6.1 Function selection
Table 3. Function selection[1] Inputs OE L L L L L L 1, 3, 5 and 7 (odd) L L L L L L Don't care
[1]
Number of inputs HIGH 0, 2, 4, 6 and 8 (even)
Data I/O T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X PARITY H L H L H L L H H L H L Z
Output ERROR Z Z H L L H Z Z L H H L Z Mode transmit transmit receive receive receive receive transmit transmit receive receive receive receive 3-state
H
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state.
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74ABT657
Octal transceiver with parity generator/checker; 3-state
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IOK IO Tj Tstg
[1] [2]
Parameter supply voltage input voltage output voltage input clamping current output clamping current output current junction temperature storage temperature
Conditions
[1]
Min -0.5 -1.2 -0.5 -18 -50 [2]
Max +7.0 +7.0 +5.5 128 150 +150
Unit V V V mA mA mA C C
output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state
[1]
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
Table 5. Symbol VCC VI VIH VIL IOH IOL t/V Tamb Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current input transition rise and fall rate ambient temperature in free air Conditions Min 4.5 0 2.0 -32 0 -40 Typ Max 5.5 VCC 0.8 64 5 +85 Unit V V V V mA mA ns/V C
74ABT657_3
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74ABT657
Octal transceiver with parity generator/checker; 3-state
9. Static characteristics
Table 6. Static characteristics Conditions Min VIK VOH input clamping voltage HIGH-level output voltage VCC = 4.5 V; IIK = -18 mA VI = VIL or VIH VCC = 4.5 V; IOH = -3 mA VCC = 5.0 V; IOH = -3 mA VCC = 4.5 V; IOH = -32 mA VOL II LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH input leakage current VCC = 5.5 V; VI = GND or 5.5 V control pins data pins IOFF IO(pu/pd) IOZ power-off leakage current power-up/power-down output current VCC = 0 V; VI or VO 4.5 V VCC = 2.0 V; VO = 0.5 V; VI = GND or VCC; OE HIGH VO = 2.7 V VO = 0.5 V ILO IO ICC output leakage current output current supply current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC VCC = 5.5 V; VO = 2.5 V VCC = 5.5 V; VI = GND or VCC outputs HIGH-state outputs LOW-state outputs disabled ICC additional supply current per input pin; VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND outputs enabled outputs 3-state, one data input outputs 3-state; one enable input CI CI/O
[1] [2] [3]
[3] [2] [1]
Symbol Parameter
25 C Typ -0.9 3.5 4.0 2.6 0.42 Max 0.55 -1.2 2.5 3.0 2.0 -
-40 C to +85 C Unit Min -1.2 2.5 3.0 2.0 Max 0.55 V V V V V
-
0.01 5 5.0 5.0
1.0 100 100 50
-
1.0 100 100 50
A A A A
OFF-state output current VCC = 5.5 V; VI = VIL or VIH -180 5.0 -5.0 5.0 -100 0.5 20 0.5 50 -50 50 -50 250 30 250 -180 50 -50 50 -50 250 30 250 A A A mA A mA A
-
0.5 50 0.5 4 7
1.5 250 1.5 -
-
1.5 250 1.5 -
mA A mA pF pF
input capacitance
VI = 0 V or VCC
input/output capacitance outputs disabled; VO = 0 V or VCC
This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V 10 %, a transition time of up to 100 s is permitted. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V.
74ABT657_3
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Product data sheet
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74ABT657
Octal transceiver with parity generator/checker; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 9. Symbol Parameter Conditions 25 C; VCC = 5.0 V Min tPLH LOW to HIGH propagation delay An to Bn or Bn to An; see Figure 6 An to PARITY; see Figure 5 and 6 ODD/EVEN to PARITY and ERROR; see Figure 5 and 6 Bn to ERROR; see Figure 5 and 6 PARITY to ERROR; see Figure 5 and 6 tPHL HIGH to LOW propagation delay An to Bn or Bn to An; see Figure 6 An to PARITY; see Figure 5 and 6 ODD/EVEN to PARITY and ERROR; see Figure 5 and 6 Bn to ERROR; see Figure 5 and 6 PARITY to ERROR; see Figure 5 and 6 tPZH tPZL tPHZ tPLZ OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay see Figure 7 and 8 see Figure 7 and 8 see Figure 7 and 8 see Figure 7 and 8
[1]
-40 C to +85 C; Unit VCC = 5.0 V 0.5 V Min 1.1 2.5 1.7 3.9 2.7 1.2 2.8 1.9 4.0 3.2 1.3 1.9 2.4 2.2 Max 4.6 8.1 5.3 12.3 7.7 4.3 8.9 5.8 12.9 8.1 6.5 6.5 6.2 7.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Typ 2.5 5.1 3.5 7.3 4.5 3.0 5.0 3.7 7.9 5.2 3.6 4.2 3.6 3.4
Max 4.1 6.7 4.6 10.2 5.9 3.9 7.4 5.1 10.5 6.7 5.5 5.3 5.6 7.3
1.1 2.5 1.7 3.9 2.7 1.2 2.8 1.9 4.0 3.2 1.3 1.9 2.4 2.2
[1]
[1]
These delay times reflect the 3-state recovery time only and do not include the delay through the buffers and the parity check circuitry which affect the ERROR output. To ensure valid information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the ERROR pin (B to A) + (A to PARITY).
74ABT657_3
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Product data sheet
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74ABT657
Octal transceiver with parity generator/checker; 3-state
11. Waveforms
VI
An, Bn, ODD/EVEN PARITY GND
VM
VM
tPHL
VOH
tPLH
PARITY, ERROR
VOL
VM
VM
001aae829
VM = 1.5 V
Fig 5.
Propagation delay for inverting output
VI
An, Bn, ODD/EVEN PARITY GND
VM
VM
tPLH
VOH
tPHL
An, Bn, PARITY, ERROR
VOL
VM
VM
001aae830
VM = 1.5 V
Fig 6.
Propagation delay for non-inverting output
VI
OE GND
VM
VM
tPZH
VOH
tPHZ
VOH - 0.3 V VM
An, Bn, PARITY, ERROR GND
001aae831
VM = 1.5 V
Fig 7.
3-state output enable time to HIGH-level and output disable time from HIGH-level
74ABT657_3
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Product data sheet
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74ABT657
Octal transceiver with parity generator/checker; 3-state
VI
OE GND
VM
VM
tPZL 3.5 V An, Bn, PARITY, ERROR
VOL VM
tPLZ
VOL + 0.3 V
001aae832
VM = 1.5 V
Fig 8.
3-state output enable time to LOW-level and output disable time from LOW-level
VI negative pulse 0V
tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW
001aai298
90 %
VEXT VCC VI VO DUT
RT CL RL RL
G
VI positive pulse 0V
90 % VM 10 %
mna616
a. Input pulse definition
Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
b. Test circuit
RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
Fig 9. Table 8. Input VI 3.0 V
Test circuit for measuring switching times Test data Load fI 1 MHz tW 500 ns tr, tf 2.5 ns CL 50 pF RL 500 VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V
74ABT657_3
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Product data sheet
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74ABT657
Octal transceiver with parity generator/checker; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT137-1 (SO24)
74ABT657_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT340-1 (SSOP24)
74ABT657_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
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NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT355-1 (TSSOP24)
74ABT657_3 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
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Octal transceiver with parity generator/checker; 3-state
13. Abbreviations
Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model
14. Revision history
Table 10. Revision history Release date 20100315 Data sheet status Product data sheet Change notice Supersedes 74ABT657_2 Document ID 74ABT657_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. DIP 24 (SOT222-1) package removed from Section 3 "Ordering information" and Section 12 "Package outline". Product specification Product specification 74ABT657 -
74ABT657_2 74ABT657
20041027 19951211
74ABT657_3
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Octal transceiver with parity generator/checker; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
74ABT657_3
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 -- 15 March 2010
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74ABT657
Octal transceiver with parity generator/checker; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT657_3
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74ABT657
Octal transceiver with parity generator/checker; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 March 2010 Document identifier: 74ABT657_3

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